Technical Field
The present disclosure relates generally to timing analyses of circuit designs, and more specifically, to methods which provide prioritized path tracing in a statistical timing analysis based on values projected from a statistical edge slack for each input edge to a given merge point in a statistical timing graph.
Related Art
Static timing analysis (STA) is used to compute the expected timing of an integrated circuit (IC) to identify problem areas of an integrated circuit during the design phase and in advance of actual fabrication. Timing runs in STA simulate the timing of the IC to determine whether or not the IC meets various timing constraints and, therefore, is likely to operate properly if fabricated in accordance with the tested design.
Deterministic static timing analysis (DSTA) propagates timing value entries, such as arrival times (ATs), required arrival times (RATs), and slews, along with any other timing related quantities (guard times, adjusts, asserts, slacks, etc.), in a timing graph as single valued deterministic data. DSTA covers a single corner of a space of process variations with each individual timing run. A corner represents a particular combination of input values for a parameter that may include temperature of the circuit, input voltage, and other manufacturing parameters of an IC. To evaluate the effect that a given parameter will have on timing, multiple DSTA timing runs must be executed with parameters that affect timing set at several maximum and minimum corners, such as high and low temperatures, high and low voltages, and various processing conditions. For example, DSTA timing runs may compare a worst case corner characterized by a combination of high input voltage, a high operating temperature, and the worst manufacturing parameters with a best case corner characterized by a combination of a low input voltage, a low operating temperature, and the best manufacturing parameters.
Timing values are computed for a timing graph at each node based upon the ATs, which define the time (or the time distribution) at which a given signal arrives at a timing point, and the RATs, which defines the time (or the time distribution) at which the signal is required to get to the timing point, in order to meet the timing requirements. These ATs and RATs are used to compute timing metrics in the form of slacks at nodes (RAT minus AT for late signals and AT minus RAT for early signals). A negative value for either a late mode slack or an early mode slack indicates a timing constraint violation. As a check of the performance of the integrated circuit design, DSTA timing runs may examine many or all of the corners and the IC design may be iteratively adjusted until all of the corners pass the timing tests. These results reflect the extreme performance bounds of the integrated circuit and may require numerous timing runs to fully explore the space of process variations. Even then, the results may be overly pessimistic and misleading for optimization tools.
Statistical static timing analysis (SSTA) propagates timing value entries as random variables with known probability distribution functions, or their approximation, instead of as scalar deterministic data (e.g., under DSTA). SSTA may calculate a result, for example, a delay and/or output slew, for the propagated statistical distribution functions of input slew and (output) load. A single timing run using block-based SSTA predicts the performance of the integrated circuit over the entire space of process variations. In contrast, a single timing run using DSTA merely predicts a single corner of the space of process variations. Consequently, in order to close or meet timing requirements, a single SSTA timing run may replace multiple DSTA timing runs. For example, assuming the existence of N parameters (i.e., variables or sources of variation) and two corners per parameter, 2N corners would have to be individually analyzed by discrete DSTA timing runs to match the effectiveness of a single SSTA run. Hence, SSTA is far more computationally efficient than DSTA.
A test run that passes in a single process corner under a DSTA timing run may actually fail without detection in one or more other performance-limiting corners in the process space, which a SSTA timing run would reveal. SSTA also reduces pessimism because of the statistical techniques inherent in this approach. For example, the propagation of known independently random terms in SSTA allows for taking the square root of the sum of the squares of random quantities (RSSing) between each propagation state, rather than straight summation as in DSTA. Finally, information regarding the probability of particular failure modes may be obtained in SSTA, as opposed to DSTA that merely indicates a binary pass/fail condition. SSTA may allow for very low probability fails to be ignored while also allowing for a more aggressive clipping of the statistical tails when used with at-speed tests.
A challenge with the conventional deterministic approach is that, when tracing backward from an end point of a timing graph to one of several possible source points, a testing regime can include modeling and selecting one of multiple input edges leading into the merge point. A final node in a timing graph can refer to a node at which a signal has completely propagated through an IC, a node where a timing check or test (i.e., Setup/Hold/Pulse-width) is performed, and/or any other node which is manually or automatically defined as being an end point. In DSTA, path tracing from a merge point can simply involve determining an input edge with the lowest-value deterministic-slack and tracing back from this particular input edge before others. However, in SSTA, each input edge is variability dependent. In other words, each input edge can be modeled as a statistical distribution. For example, the fact that an output load is fabrication process, voltage, temperature (PVT) dependent indicates that loads can be modeled in a statistical fashion. Consequently, attempting to prioritize each input edge based on statistically modeled parameters can introduce a new dimension of complexity in statistical macro-modeling and analysis of a timing graph.